Asynchronous FIFO verification
Check for lost, duplicated, or reordered data as it moves between independent clocks.
How the check works
Different clocks. The same data, in order.
Write side
One clock drives words into the FIFO, with pauses.
FIFO buffer
The queue transfers data between the two clock domains.
Read side
An independent clock reads words; a checker compares their order and values.
Concept illustration. The simulation checks the agreed clock settings and stimulus. It does not model electrical metastability or replace structural CDC analysis.
What you receive
- A testbench and logs across clock ratios.
- An integrity check for lost, duplicated, or reordered words.
- Bound pointer and synchronizer assertions where included in the agreed scope.
- The tested clock settings, stimulus, and known limits.
When this is useful
- A design adds a FIFO or handshake between two clock domains.
- An intermittent data error appears only on hardware.
- A CDC review needs checks that keep running in regression.
Problem, approach, and required inputs
The problem
When data moves between two independent clocks, a signal can be sampled while it is changing. This is a clock domain crossing, or CDC. These bugs rarely show up in single clock simulation, and they are very hard to debug in silicon.
What we do
We drive each side from its own clock with random pauses on both sides and check that every item arrives once and in order. Bound assertions can check pointer movement and synchronizer staging during the regression. The agreed scope defines the clock pairs, reset scenarios, and stimulus to check. This is a functional simulation service; it does not replace structural CDC analysis or electrical sign off.
Inputs agreed after scoping and NDA
- The crossing or FIFO.
- The two clocks and their frequency ranges.
Related public demonstration
Public demonstration, not a client result
A FIFO bug the random test missed
A deliberately broken full-write guard exposes a gap in the original test. A directed regression catches it.
More problems you can reproduce
Technical details
How the result is checked
The integrity check fails the run if any item is lost or duplicated. Simulation logs are retained for inspection, with run settings and instructions to repeat the tests.
Tools used for this kind of work
- cocotb
- Icarus Verilog
- SystemVerilog Assertions
- Verilator
Scripts are handed over as agreed in the scope. If we have not tested your simulator or flow, the scope says so.
Discuss this problem.
Tell us what you are trying to verify and what is blocking you. A person replies, and the scope comes back in writing after a call.
Discuss a verification problem