Results you can inspect. Checks you can rerun.

These are public demonstrations, not client results. Each page records the problem, the checked result, the reproduction command, and the limits of what the example proves.

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Integration and subsystem examples

Explore the tested configuration, interacting behaviours, and recorded evidence. Each example has a defined scope.

Historical bugChecks passed

A timer write triggers an interrupt at rollover

An ordinary timer test passes. A write at the carry boundary reproduces a historical upstream defect and its spurious interrupt.

Problem, evidence, and limits

Architectural testsChecks passed

Architectural tests, from generation to RTL results

Generate and run the exact ACT4 matrix for a pinned CV32E40P configuration.

Problem, evidence, and limits

Regression automationChecks passed

A green regression needs a complete report

Run three pinned RTL projects and reject incomplete, stale, or inconsistent evidence before reporting success.

Problem, evidence, and limits

Debug, interrupts, exceptionsChecks passed

A brief halt request is lost at a control boundary

Ordinary tests pass, but requests arriving during a stall, exception flush, or debug return expose seeded faults in a real RISC-V controller.

Problem, evidence, and limits

FIFO assertionsChecks passed

Check the FIFO rules while data moves

A stale full decision can allow one write too many. Concurrent traffic and independent pointer assertions expose the error.

Problem, evidence, and limits

Smaller examples of the method

Compact teaching designs explain individual checks. They demonstrate the workflow and are not evidence of complex IP verification.

Bug to verified fixChecks passed

From a missed timer interrupt to a verified fix

A RISC-V machine timer with a seeded bug, taken from failing test to counterexample, root cause, proven fix, and closed coverage holes.

Problem, evidence, and limits

Formal proofChecks passed

A safety property proven for every reachable state

A traffic light controller that must never let both directions go at once.

Problem, evidence, and limits

Clock domain crossingChecks passed

A FIFO bug the random test missed

A deliberately broken full-write guard exposes a gap in the original test. A directed regression catches it.

Problem, evidence, and limits

Python testbenchChecks passed

A Python testbench that checks itself

A reference model, random stimulus, and a coverage count per operation.

Problem, evidence, and limits

BackpressureChecks passed

Keep data intact when the receiver pauses

A buffer must hold its output while the receiver is blocked. A deliberately broken version overwrites it, and the test catches the change.

Problem, evidence, and limits

Reset recoveryChecks passed

Stop cancelled work from returning after reset

Reset arrives with requests still in flight. The test checks that cancelled responses disappear and new work returns in order.

Problem, evidence, and limits

ArbitrationChecks passed

Give every waiting requester a turn

An arbiter may grant access to only one requester and still be unfair. A persistent request test exposes starvation in a fixed priority variant.

Problem, evidence, and limits

UVM testbenchChecks passed

A UVM scoreboard that detects a mismatch

Execute the UVM classes and check every transaction against a reference model.

Problem, evidence, and limits

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