A FIFO bug the random test missed

A deliberately broken full-write guard exposes a gap in the original test. A directed regression catches it.

Checks passed

Public demonstration

This is not a client result. The recorded command and check status appear below.

Recorded outcome

The directed test catches the seeded corruption that the original random test misses. Both tests pass on the correct RTL at write/read clock periods of 10/13, 17/10, and 7/19 ns.

What was checked

Problem: The original random test sends 256 words but avoids writes while the FIFO is full. It therefore misses a deliberately introduced bug that lets a rejected write overwrite unread data.
Scope: One asynchronous FIFO with 8-bit words and depth 16. Functional simulation covers ordering, full and empty rejection, pointer wrap, and coordinated reset while idle with data still queued. This is a seeded public demonstration, not a client result.
Approach: The reproducer removes the full-write memory guard in a temporary RTL copy. The original random test still passes, but the new directed test fills the queue, attempts rejected writes, then detects corrupted data with ORDER_MISMATCH. The same tests run against the correct guarded implementation already in the repository.
Evidence: The repository includes logs, JUnit results, a result summary, and CI for the expected failure and passing cases. Each test has a 100 microsecond simulation limit and each build/run process has a 90 second wall limit. Missing results and timeouts are not passes.

Scope and limits

What these checks do not establish.

The bug is deliberately introduced into a temporary copy. No new defect in the committed FIFO RTL is claimed.
Only 8-bit words, depth 16, three clock pairs, and one fixed random seed are tested. This is not exhaustive verification.
Reset is coordinated while both sides are idle. Independent reset and reset during a transfer are not verified.
Digital simulation does not model electrical metastability or physical Gray-bus skew. It does not replace structural CDC analysis or formal proof.
The reusable sync_2ff module is compiled but is not instantiated by this FIFO, so these runs do not independently verify it.

Reproduce and inspect

Recorded verification status

Verified from a fresh clone of merged revision 72d8122 on 15 September 2026 with cocotb 2.1.0 and Icarus Verilog 13.0. The seeded variant has one expected directed failure; the correct RTL passes both tests at all three tested clock pairs.

Recorded commandcdc-verification

python3 -m venv .venv
. .venv/bin/activate
pip install -r requirements.txt
python scripts/reproduce.py

Filesrtl/async_fifo.svcorrect guarded-write implementationtb/test_async_fifo.pyrandom and directed regressionscripts/reproduce.pytemporary mutant and passing runsevidence/audit-2026-09-15/committed logs and results

Next steps

Service: Asynchronous FIFO verification Other examples

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