RISC-V architectural tests (ACT4)
Compare your core against architectural expectations, with a result for every test in the agreed matrix.
How the check works
Keep the configuration and evidence together.
Generate the tests
Use the pinned configuration and reference expectations.
Run the RTL
Build the simulator and execute every named test.
Account for every result
Record each outcome, its inputs, and any remaining mismatch.
Concept illustration. The public result covers the named ACT4 matrix on one CV32E40P configuration. It is not a general certification claim.
What you receive
- The agreed test matrix and pinned generation configuration.
- A pass, fail, or unresolved outcome for every expected test.
- Integration scripts, raw logs, and hashes connecting inputs to results.
- Reproduction instructions and a clear statement of untested features.
When this is useful
- You need architectural test results for a named RISC-V core configuration.
- An ACT4 run fails and the source of the mismatch is unclear.
- You need to repeat the same architectural checks after an RTL change.
Problem, approach, and required inputs
The problem
A processor that runs a program may still differ from its architectural requirements. The core configuration, generated expectations, simulator integration, and test results all need to agree.
What we do
We pin the source and tool configuration, generate architectural tests with reference expectations, integrate the test platform, and execute the agreed matrix on RTL. We investigate failures and report each outcome with the source revisions, commands, and limits.
Inputs agreed after scoping and NDA
- The core revision, ISA configuration, privilege features, and simulator.
- The platform interface, memory map, and testbench integration.
- The test matrix and any known unsupported features.
Related public demonstration
Public demonstration, not a client result
Architectural tests, from generation to RTL results
Generate and run the exact ACT4 matrix for a pinned CV32E40P configuration.
Technical details
How the result is checked
The public CV32E40P v2 RV32IMC example generates a fresh ACT4 matrix, builds the simulator, and passes all 94 named RTL tests. It checks that the complete matrix ran and that each result is unambiguous. This is architectural test evidence for one configuration, not general compliance certification.
Tools used for this kind of work
- RISC-V ACT4
- Sail reference model
- Verilator
- RISC-V GCC
- Python
Scripts are handed over as agreed in the scope. If we have not tested your simulator or flow, the scope says so.
Discuss this problem.
Tell us what you are trying to verify and what is blocking you. A person replies, and the scope comes back in writing after a call.
Discuss a verification problem