Keep data intact when the receiver pauses
A buffer must hold its output while the receiver is blocked. A deliberately broken version overwrites it, and the test catches the change.
Public demonstration
This is not a client result. The recorded command and check status appear below.
Recorded outcome
The correct buffer passes all four tested configurations. The deliberately broken buffer fails the data stability check in all four. The tests also check that input and output can transfer on the same clock edge.
What was checked
- Problem
- A simple transfer test can miss what happens when a receiver pauses. If a full buffer still accepts new input, the waiting word can be replaced before the receiver takes it.
- Scope
- One original, single entry buffer with a ready and valid interface. A transfer requires both signals at the clock edge. Tested width and seed pairs are 1/7, 8/1, 8/2025, and 17/99. Reset is synchronous and discards the waiting word.
- Approach
- The source holds its word until an accepted transfer. A queue predicts output order while the receiver pauses. Directed checks exercise occupied reset, output stability, and simultaneous transfers. An always ready mutant deliberately ignores the full buffer and fails the same stability check.
- Evidence
- The repository includes RTL, a queue scoreboard, fixed seeds, command logs, source hashes, and measured compile and simulation times. The runner requires the intended failure diagnostic; a timeout or unrelated failure does not qualify. A separate default configuration synthesis check is recorded.
Scope and limits
What these checks do not establish.
- This is original educational RTL with a deliberately introduced defect, not a client finding or production IP.
- One ready and valid channel does not implement or verify the complete AXI protocol.
- The finite simulation checks do not establish a formal proof, CDC safety, asynchronous reset behaviour, or timing closure.
- Only the listed width and seed pairs were tested. Process runtimes are measurements of these small examples, not delivery estimates.
Reproduce and inspect
Recorded verification status
Rerun from public GitHub revision 7c4c191 on 15 September 2026 with Python 3.9.6 and Icarus Verilog 13.0. Four correct configurations pass; four seeded variants fail with the required stability diagnostic. Three runner regression tests also pass.
git clone https://github.com/Rivoryxa-Technologies/ready-valid-verification
cd ready-valid-verification
# Install Python 3.9+ and Icarus Verilog first.
python3 run.py
python3 -m unittest discover -s tests -vrtl/ready_valid_buffer.svcorrect one entry bufferrtl/ready_valid_buffer_mutant.svdeliberately broken comparisontb/tb_ready_valid.svstimulus and queue scoreboardrun.pyreproduction and measured resultsrecorded/2026-09-15/reviewed logs and source hashesWant this method on your design?
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